www.kersemi,com 1 power mosfet irfr010, SIHFR010 features ? low drive current ? surface mount ?fast switching ? ease of paralleling ? excellent temperature stability ? compliant to rohs directive 2002/95/ec description the power mosfet technology is the key to vishays advanced line of power mosfet transistors. the efficient geometry and unique processing of this latest state of the art design achieves: very low on-state resistance combined with high transconductance; superior reverse energy and diode recove ry dv/dt capability. the power mosfet transistors also feature all of the well established advantages of mosfets such as voltage control, very fast switchin g, ease of paralleling and temperature stability of the electrical parameters. surface mount packages enha nce circuit performance by reducing stray inductances and capacitance. the dpak (to-252) surface mount package brings the advantages of power mosfets to high volume applications where pc board surface mounting is de sirable. the surface mount option irfr9012, sihfr9012 is provided on 16 mm tape. the straight lead option irfu9012, sihfu9012 of the device is called the ipak (to-251). they are well suited for applications where limited heat dissipation is required such as, computers and peripherals, telecommunication equipment, dc-to-dc converters, and a wide range of consumer products. notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. v dd = 25 v, starting t j = 25 c, l = 100 h, r g = 25 ? . c. i sd ? 8.2 a, di/dt ? 130 a/s, v dd ? 40 v, t j ? 150 c. d. 1.6 mm from case. e. when mounted on 1" square pcb (fr-4 or g-10 material). product summary v ds (v) 50 r ds(on) ( ? )v gs = 10 v 0.20 q g (max.) (nc) 10 q gs (nc) 2.6 q gd (nc) 4.8 configuration single n-channel mosfet g d s dpak (to-252) s d g ordering information package dpak (to-252) lead (pb)-free irfr010pbf SIHFR010-e3 snpb irfr010 SIHFR010 absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 50 v gate-source voltage v gs 20 continuous drain current v gs at 10 v t c = 25 c i d 8.2 a t c = 100 c 5.2 pulsed drain current a i dm 33 avalanche current b i as 1.5 linear derating factor 0.20 w/c maximum power dissipation t c = 25 c p d 25 w peak diode recovery dv/dt c dv/dt 2.0 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 300 d document number: 91420 www.vishay.com s10-1510-rev. a, 19-jul-10 1 power mosfet irfr010, SIHFR010 vishay siliconix features ? low drive current ? surface mount ?fast switching ? ease of paralleling ? excellent temperature stability ? compliant to rohs directive 2002/95/ec description the power mosfet technology is the key to vishay?s advanced line of power mosfet transistors. the efficient geometry and unique processing of this latest ?state of the art? design achieves: very low on-state resistance combined with high transconductance; superior reverse energy and diode recove ry dv/dt capability. the power mosfet transistors also feature all of the well established advantages of mosfet?s such as voltage control, very fast switchin g, ease of paralleling and temperature stability of the electrical parameters. surface mount packages enha nce circuit performance by reducing stray inductances and capacitance. the dpak (to-252) surface mount package brings the advantages of power mosfet?s to high volume applications where pc board surface mounting is de sirable. the surface mount option irfr9012, sihfr9012 is provided on 16 mm tape. the straight lead option irfu9012, sihfu9012 of the device is called the ipak (to-251). they are well suited for applications where limited heat dissipation is required such as, computers and peripherals, telecommunication equipment, dc-to-dc converters, and a wide range of consumer products. notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. v dd = 25 v, starting t j = 25 c, l = 100 h, r g = 25 : . c. i sd d 8.2 a, di/dt d 130 a/s, v dd d 40 v, t j d 150 c. d. 1.6 mm from case. e. when mounted on 1" square pcb (fr-4 or g-10 material). product summary v ds (v) 50 r ds(on) ( : )v gs = 10 v 0.20 q g (max.) (nc) 10 q gs (nc) 2.6 q gd (nc) 4.8 configuration single n-channel mosfet g d s dpak (to-252) s d g ordering information package dpak (to-252) lead (pb)-free irfr010pbf SIHFR010-e3 snpb irfr010 SIHFR010 absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 50 v gate-source voltage v gs 20 continuous drain current v gs at 10 v t c = 25 c i d 8.2 a t c = 100 c 5.2 pulsed drain current a i dm 33 avalanche current b i as 1.5 linear derating factor 0.20 w/c maximum power dissipation t c = 25 c p d 25 w peak diode recovery dv/dt c dv/dt 2.0 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 300 d * pb containing terminations are not rohs compliant, exemptions may apply
www.kersemi.com 2 irfr010, SIHFR010 notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. pulse width ? 300 s; duty cycle ? 2 %. thermal resistance ratings parameter symbol min. typ. max. unit maximum junction-to-ambient r thja - - 110 c/w case-to-sink r thcs -1.7- maximum junction-to-case (drain) r thjc --5.0 specifications (t j = 25 c, unless otherwise noted) parameter symbol test condi tions min. typ. max. unit static drain-source brea kdown voltage v ds v gs = 0 v, i d = 250 a 50 - - v gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 v gate-source leakage i gss v gs = 20 v - - 500 na zero gate voltage drain current i dss v ds = 50 v, v gs = 0 v - - 250 a v ds = 40 v, v gs = 0 v, t j = 125 c - - 1000 drain-source on-state resistance r ds(on) v gs = 10 v i d = 4.6 a b - 0.16 0.20 ? forward transconductance g fs v ds ? 50 v, i d = 3.6 a 2.1 3.1 - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 10 - 250 - pf output capacitance c oss - 150 - reverse transfer capacitance c rss -29- total gate charge q g v gs = 10 v i d = 7.3 a, v ds = 40 v, see fig. 6 and 13 b -6.710 nc gate-source charge q gs -1.82.6 gate-drain charge q gd -3.24.8 turn-on delay time t d(on) v dd = 25 v, i d = 7.3 a, r g = 24 ? , r d = 3.3 ? , see fig. 10 b -1117 ns rise time t r -3350 turn-off delay time t d(off) -1218 fall time t f -2335 internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact c -4.5- nh internal source inductance l s -7.5- drain-source body diode characteristics continuous source-dr ain diode current i s mosfet symbol showing the integral reverse p - n junction diode --8.2 a pulsed diode forward current a i sm --33 body diode voltage v sd t j = 25 c, i s = 8.2 a, v gs = 0 v b --1.6v body diode reverse recovery time t rr t j = 25 c, i f = 7.3 a, di/dt = 100 a/s b 41 86 190 ns body diode reverse recovery charge q rr 0.15 0.33 0.78 c forward turn-on time t on intrinsic turn-on time is negligible (turn-on is dominated by l s and l d ) d s g s d g www.vishay.com document number: 91420 2 s10-1510-rev. a, 19-jul-10 irfr010, SIHFR010 vishay siliconix notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. pulse width d 300 s; duty cycle d 2 %. thermal resistance ratings parameter symbol min. typ. max. unit maximum junction-to-ambient r thja - - 110 c/w case-to-sink r thcs -1.7- maximum junction-to-case (drain) r thjc --5.0 specifications (t j = 25 c, unless otherwise noted) parameter symbol test condi tions min. typ. max. unit static drain-source brea kdown voltage v ds v gs = 0 v, i d = 250 a 50 - - v gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 v gate-source leakage i gss v gs = 20 v - - 500 na zero gate voltage drain current i dss v ds = 50 v, v gs = 0 v - - 250 a v ds = 40 v, v gs = 0 v, t j = 125 c - - 1000 drain-source on-state resistance r ds(on) v gs = 10 v i d = 4.6 a b - 0.16 0.20 : forward transconductance g fs v ds t 50 v, i d = 3.6 a 2.1 3.1 - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 10 - 250 - pf output capacitance c oss - 150 - reverse transfer capacitance c rss -29- total gate charge q g v gs = 10 v i d = 7.3 a, v ds = 40 v, see fig. 6 and 13 b -6.710 nc gate-source charge q gs -1.82.6 gate-drain charge q gd -3.24.8 turn-on delay time t d(on) v dd = 25 v, i d = 7.3 a, r g = 24 : , r d = 3.3 : , see fig. 10 b -1117 ns rise time t r -3350 turn-off delay time t d(off) -1218 fall time t f -2335 internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact c -4.5- nh internal source inductance l s -7.5- drain-source body diode characteristics continuous source-dr ain diode current i s mosfet symbol showing the integral reverse p - n junction diode --8.2 a pulsed diode forward current a i sm --33 body diode voltage v sd t j = 25 c, i s = 8.2 a, v gs = 0 v b --1.6v body diode reverse recovery time t rr t j = 25 c, i f = 7.3 a, di/dt = 100 a/s b 41 86 190 ns body diode reverse recovery charge q rr 0.15 0.33 0.78 c forward turn-on time t on intrinsic turn-on time is negligible (turn-on is dominated by l s and l d ) d s g s d g
www.kersemi,.com 3 irfr010, SIHFR010 typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature document number: 91420 www.vishay.com s10-1510-rev. a, 19-jul-10 3 irfr010, SIHFR010 vishay siliconix typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature
www.kersemi.com 4 irfr010, SIHFR010 fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area www.vishay.com document number: 91420 4 s10-1510-rev. a, 19-jul-10 irfr010, SIHFR010 vishay siliconix fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area
www.kersemi.com 5 irfr010, SIHFR010 fig. 9 - maximum drain curre nt vs. case temperature fig. 10 - breakdown voltage vs. temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f document number: 91420 www.vishay.com s10-1510-rev. a, 19-jul-10 5 irfr010, SIHFR010 vishay siliconix fig. 9 - maximum drain curre nt vs. case temperature fig. 10 - breakdown voltage vs. temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f
www.kersemi.com 6 irfr010, SIHFR010 fig. 11 - maximum effective transient thermal impedance, junction-to-case fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms r g i as 0.01 t p d.u.t l v ds + - v dd 10 v var y t p to obtain required i as i as v ds v dd v ds t p www.vishay.com document number: 91420 6 s10-1510-rev. a, 19-jul-10 irfr010, SIHFR010 vishay siliconix fig. 11 - maximum effective transient thermal impedance, junction-to-case fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms r g i as 0.01 t p d.u.t l v ds + - v dd 10 v var y t p to obtain required i as i as v ds v dd v ds t p
www.kersemi.com 7 irfr010, SIHFR010 fig. 12c - typical transconductance vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit q gs q gd q g v g charge v gs d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + - document number: 91420 www.vishay.com s10-1510-rev. a, 19-jul-10 7 irfr010, SIHFR010 vishay siliconix fig. 12c - typical transconductance vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit q gs q gd q g v g charge v gs d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + -
www.kersemi.com 8 irfr010, SIHFR010 fig. 14 - for n-channel p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage rever s e recovery current body diode forward current v gs = 10 v a i s d driver gate drive d.u.t. l s d waveform d.u.t. v d s waveform inductor current d = p.w. period + - + + + - - - peak dio d e recovery d v/ d t test circuit v dd ? dv/dt controlled by r g ? driver s ame type a s d.u.t. ? i s d controlled by duty factor d ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low s tray inductance ? g round plane ? low leakage inductance current tran s former r g note a. v gs = 5 v for logic level device s v dd www.vishay.com document number: 91420 8 s10-1510-rev. a, 19-jul-10 irfr010, SIHFR010 vishay siliconix fig. 14 - for n-channel vishay siliconix maintains worldwide manufa cturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91420 . p.. period d/dt iode recovery dv/dt ripple ody diode forward drop reapplied voltage rever s e recovery current ody diode forward current v s v a s river gate drive ..t. l s waveform ..t. v s waveform nductor current p.. period peak io d e recovery d v/ d t test ircuit v dv/dt controlled by r g river s ame type a s ..t. s controlled by duty factor ..t. device under te s t ..t. ircuit layout con s ideration s ow s tray inductance round plane ow leakage inductance current tran s former r g ote a. v s v for logic level device s v
|
